Cost-Effective use of HDI PCB technology

  • New

Fine-pitch BGAs create a necessary complication with HDI PCB where the design rules are chosen to not provide clearance for staggered blind vias. 

High Density Interconnect (HDI) PCB manufacturing technology


■ Also known as microvia HDI PCB technology, or Sequential Build-Up technology (or simply ‘Build-Up’)…


– uses ‘microvias’ 6 thou (0.15mm) diameter or less, so can achieve twice the number of pins/area than THP…
– and which only connect between necessary board layers, so don’t constrain routing on other layers

■ All of which means they can significantly reduce the number of PCB layers required…

– especially where THP would require 10 layers or more


Microvias are closed at one end…


– so don’t steal solder during reflowing, allowing via-in-pad layouts…
● good for EMC because this reduces the inductances associated with power supply decoupling

■ But if blind microvias-in-pads are not completely filled/capped to provide a planar copper surface…
– solder paste printed over them traps little air bubbles…
– which expand and ‘pop’during soldering, possibly causing poor solder joints

 

 

HDI PCB benefits

HDI PCB techniques help to make the smallest, lightest, and least power-hungry products…
– and can be found in a wide variety of common products (including some toys)
■ Microvias are inherently more robust than THP…
– so are preferred in some hi-reliability or harsh environment applications

BGA’s PI & SI suffers from perforation of the 0V, Power planes underneath

■ The best that can be done with THP is to use suitable track-and-space (track-and-gap) layoutrules…
– to try achieve a complete mesh or grid over the area covered by the BGA’s solder pads…

HDI 0V planes aren’t perforated…

– and so create solid, continuous 0V/Power plane pairs under BGAs, with lower series inductances, higher mutual inductances and higher capacitances which all improves decoupling…
● improving both PI and EMC
– and they provide lower and more constant return path inductances…
● improving both SI and EMC
■ Where microvias do perforate a plane, the gaps they create are very small…
– so the effects on SI, PI and EMC are small

HDI’s additional EMC benefits include…

– via-in-pad reduces decoupling inductances, pushing PDN resonances to higher frequencies…
– shorter traces become efficient ‘accidental antennas’ at higher frequencies…
– smaller PCBs become efficient “accidental patch antennas” at higher frequencies…
– shorter traces may not need to be treated as transmission lines…
– less perforated 0V and Power planes have improved‘image plane’ effect so have higher shielding effectiveness

HDI makes it possible to use the smallest IC package styles, and obtain their EMC benefits, e.g…

– Miniature or Micro BGA (especially with ball pitch <1mm)
– DCA (direct chip attach)
– Flip-chip
– CSP (chip scale packaging)
– TAB (tape automated bonding)
■ These very small, thin semiconductor packages have much closer proximity to the PVB’s 0V/Power planes than a regular packaged IC…
– so their ‘image plane’ effect is stronger – reducing emissions, and increasing immunity

Beware, when using chip-scale package styles!

■ Because they lack the inductances associated with bond wires and lead-frames…
– their very sharp internal switching speeds ‘leak’ higher levels of higher frequency noises into the PCB structure, making EMC worse…
– unless HDI and good EMC design techniques are used

HDI PCB  costs

■ An IPC survey in 2000 found HDI boards could be purchased for the same cost as THP…
● and not using buried vias helps reduce costs further
■ Latest advice (Mentor Graphics) is that boards needing > 8-10 layers should cost less if made in HDI…
– e.g. a high-density 18 layer THP board would only need 10 layers if using HDI…
● but even for lower densities or fewer layers, HDI’s EMC, SI and PI advantages make it more cost-effective than THP…
– focussing on the BOM cost instead of ‘overall cost of manufacture’ is a common management mistake!

Some HDI PCB stack-up issues

■ IPC Types I, II and II use a core (e.g. FR4) with FR4 or polymer ‘build-up’ layers containing microvias and/or THP vias, to keep costs low…

– but different layer materials have different temperature coefficients and rates of moisture absorbance…
● so delamination is a real possibility, especially if there is significant temperature and/or humidity cycling…
– not a problem, of course, when using same material for every layer
■ Some people say:“IPC Type IV, V, VI HDI constructions are more costly, and probably not necessary for large dense PCBs with BGA breakout and routing challenges”

Stack-ups for good PI and EMC continued...

■ Top and Bottom layers as 0V (i.e. GND) planes helps shield all the internal traces…
– with perimeter guard traces and low-cost BLS (board level shields) can make fully-shielded PCB assemblies…
● see my PCB book for more details…
– usually 30% or more BGA pins are 0V and many of the rest are Power, but microvia antipads are very small…
● so the perforation of these planes is not very great
■ Power (VCC, VDD) planes on adjacent layers create distributed (embedded) decoupling capacitances immediately below the devices: best for PI


Stack-ups for good PI and EMC continued...

■ These stackups benefit from stacked microvias, and board size, product weight/size, and overall manufacturing costs can be reduced by:
● embedded pull-up and termination resistors…
● embedded surge/transient protection…
● embedded ICs (like smart cards)…
● embedded decoupling capacitors…
● embedded high-capacitance laminates ideally less than 50µm (0.002 inch) thick between 0V/Power planes, can provide several nF per square centimetre, making it possible to eliminate all soldered decoupling capacitors (excluding ‘bulk’ caps ≥ 10µF)

 

Microvia (High Density Interconnect, HDI) PCB manufacturing technology has developed rapidly in recent years, and can now be used to reduce bare-board cost where a Through Hole Plate (THP) board would need 10 or more layers.

And microvia’s benefits for good EMC (and SI and PI) design at board level mean it can reduce overall unit-cost-of-manufacture even where THP boards would require fewer than 10 layers.

This article looks at what microvia board techniques are now available, and how they can be used to help achieve good EMC whilst reducing costs and getting to market more quickly.

Calculate
Contact us
  • Email:
    This email address is being protected from spambots. You need JavaScript enabled to view it.
Copyright © 2022 Hemeixin Electronics Co, Ltd. All Rights Reserved.