HDI Circuit Boards Design and Manufacturing

HDI circuit boards use microvias, blind and buried interconnections, thin dielectric layers, fine conductors, and sequential lamination to route more signals within a smaller PCB area. A reliable HDI PCB design begins with the component escape pattern and then defines the via structure, i+N+i stack-up, dielectric thickness, copper weight, impedance geometry, lamination count, and via-fill process. When these decisions are coordinated with an HDI PCB manufacturer before layout completion, engineers can reduce microvia cracking, registration loss, impedance deviation, resin voids, and unnecessary fabrication cost.

A practical HDI production package should define:

• Finished board thickness and tolerance
• Total copper layer count
• HDI build-up structure
• Laser microvia diameter and pad size
• Mechanical drill diameter
• Stacked or staggered microvias
• Via filling and via-in-pad requirements
• Minimum line width and spacing
• Controlled impedance targets
• Base material and glass transition temperature
• Copper foil thickness
• Surface finish
• Sequential lamination count
• Reliability and inspection class

IPC-2226A establishes design requirements and considerations for high density interconnect printed boards and microvia structures. It is used with IPC-2221, which provides general printed board design requirements. IPC-6012F covers qualification and performance requirements for rigid printed boards, including structures containing blind vias, buried vias, and microvias.

Via Technologies

Microvias

A microvia is a small blind or buried interconnection formed between adjacent or nearby copper layers. IPC technical material identifies microvias as blind or buried vias with a diameter of 150 µm or less.

Common production dimensions include:

• Laser-drilled hole diameter: 60–125 µm
• Finished microvia diameter: 50–100 µm
• Capture pad diameter: 200–300 µm
• Target pad diameter: 200–275 µm
• Dielectric depth: 50–100 µm
• Preferred aspect ratio: approximately 0.75:1 to 1:1
• Copper fill dimple: normally controlled below 15–25 µm

The operating principle is simple: a small laser-drilled via consumes less routing area than a mechanically drilled through-hole. The practical value is more routing channels between BGA pads and fewer layers required for fanout.

For a 0.40 mm pitch BGA, a 75 µm microvia with a 200–225 µm pad may support via-in-pad escape. A conventional 0.20 mm mechanical hole with a 0.45 mm pad normally cannot fit inside the same pad geometry.

Blind Vias

Blind vias connect an external layer to one or more internal layers without passing through the entire PCB.

Typical examples include:

• L1 to L2 laser microvia
• L1 to L3 stacked microvias
• L1 to L4 mechanically drilled blind via
• L12 to L11 bottom-side microvia

Blind vias reduce unused barrel length and open routing channels on deeper layers. However, mechanically drilled blind vias require sufficient drilling depth control and normally need a larger diameter than laser microvias.

Typical mechanically drilled blind-via values are:

• Drill diameter: 0.15–0.30 mm
• Finished diameter: 0.10–0.25 mm
• Aspect ratio: normally below 1:1
• Pad diameter: 0.35–0.60 mm

Buried Vias

Buried vias connect internal layers and are not visible from either external surface.

A common buried-via structure connects:

• L3 to L8 inside a 2+6+2 board
• L2 to L7 inside a 1+6+1 board
• Selected core layers beneath high-density component areas

Buried vias are drilled and plated before the final lamination cycle. Their main value is preserving external routing space and reducing through-hole congestion.

The main manufacturing limitation is process count. Each buried-via subassembly requires drilling, desmear, copper plating, imaging, inspection, and lamination before the full panel is completed.

Via Technology Comparison

Stacked vs. Staggered

Stacked Microvias

Stacked microvias are positioned directly above one another. A three-level stack from L1 to L4 contains:

• L1–L2 microvia
• L2–L3 microvia
• L3–L4 microvia

The lower microvias must normally be copper-filled before the next microvia is drilled. This creates a vertical copper column.

Stacked structures provide:

• Minimum routing footprint
• Direct vertical layer transition
• High-density via-in-pad fanout
• Simple electrical transition geometry

The production risk is concentrated stress at the copper interfaces. Stacked microvias therefore require controlled filling, flatness, target-pad registration, and thermal-cycle validation. Industry manufacturing guidance consistently treats stacked structures as more demanding than staggered alternatives.

Staggered Microvias

Staggered microvias are offset from one build-up layer to the next.

Typical offset values are:

• Minimum center-to-center offset: 250–350 µm
• Minimum copper bridge between pads: 75–100 µm
• Trace width between microvias: 75–100 µm where permitted

The staggered arrangement spreads mechanical stress and does not require every microvia to form one continuous copper column. It is generally easier to manufacture reliably, but it consumes more routing area.

Stacked vs. Staggered Comparison

Layer Stack-Ups

The i+N+i Structure

The notation i+N+i describes a symmetrical HDI PCB stack-up:

• i represents the number of sequential build-up layers on each side.
• N represents the number of layers in the central core.
• The total layer count is N + 2i.

For example:

• 1+4+1 = 6 layers
• 1+6+1 = 8 layers
• 2+4+2 = 8 layers
• 2+6+2 = 10 layers
• 3+8+3 = 14 layers

This notation is widely used by fabricators to communicate build-up complexity and lamination requirements.

Core Layers

The core, represented by N, is the conventionally laminated central structure.

The core may contain:

• Mechanically drilled through-holes
• Buried vias
• Power and ground planes
• High-speed routing layers
• Thicker dielectric materials
• Internal copper weights of 18–35 µm

A typical six-layer core may use:

• 0.10–0.20 mm dielectric between signal and reference planes
• 0.20–0.40 mm cores between lower-speed layers
• 18 µm inner copper before plating or processing
• Buried vias with 0.15–0.25 mm drills

The core provides mechanical strength and carries interconnections that do not require the fine geometry of the build-up layers.

Build-Up Layers

Build-up layers are added to the core through sequential lamination.

They normally use:

• Resin-coated copper
• Thin prepreg
• Laser-drillable dielectric
• 40–100 µm dielectric thickness
• 9–18 µm starting copper
• Laser microvias between adjacent layers

Each build-up tier usually requires:

1. Lamination
2. Laser drilling
3. Desmear and cleaning
4. Electroless copper
5. Electrolytic plating
6. Via filling
7. Surface planarization
8. Circuit imaging

A 2+N+2 HDI board therefore requires more process stages than a 1+N+1 board.

Common Configurations

Core Structural Types

Type I

IPC-2226 Type I uses one microvia layer on one or both sides of a conventional core. It may include plated through-holes but does not use buried vias.

A typical Type I structure is:

• L1–L2 microvias
• Through-holes from L1 to the bottom layer
• No internal buried-via structure

Type I provides an economical entry into HDI PCB fabrication and is suitable when one microvia tier is enough to escape the component field.

Type II

Type II also uses one microvia layer on one or both sides, but the core includes buried vias.

Typical structure:

• L1–L2 laser microvias
• Buried vias through selected core layers
• Plated through-holes where required

The buried vias create additional routing freedom under dense components without requiring a second microvia tier.

Type III

Type III uses two or more microvia layers on at least one side of the core.

Typical structures include:

• 2+4+2
• 2+6+2
• 3+6+3
• Stacked or staggered microvias

This structure supports high-I/O BGAs and more complex layer transitions but increases sequential lamination and registration requirements. IPC technical information describes Type III as using two microvia layers on one or both sides of a substrate core.

Any-Layer ELIC

ELIC means every layer interconnection. Microvias can connect adjacent layers throughout the entire board instead of only within external build-up layers.

Any-layer construction provides:

• Maximum routing freedom
• Short interconnect paths
• High via-in-pad density
• Reduced dependence on through-holes
• Support for compact modules and advanced processors

The manufacturing challenge is that nearly every layer may require laser drilling, copper filling, imaging, and lamination. Registration accumulation must be controlled across multiple process cycles.

Routing and Layout Rules

Fine Lines

Typical HDI line and space capability depends on copper thickness and process type.

Common production ranges include:

Fine-line yield is affected by:

• Starting copper thickness
• Copper-plating uniformity
• Dry-film resolution
• Etching factor
• Panel position
• Surface cleanliness
• Solder-mask registration

For 75/75 µm geometry, 9–12 µm starting copper is easier to control than 35 µm copper because less lateral copper must be etched.

Fanout and Via Pads

For a 0.50 mm pitch BGA, a practical HDI fanout may use:

• 75–100 µm microvia
• 225–275 µm via pad
• 75–100 µm trace width
• 75–100 µm spacing

For a 0.40 mm pitch BGA, common targets may tighten to:

• 60–75 µm microvia
• 180–225 µm pad
• 50–75 µm trace
• 50–75 µm spacing

The pad geometry must still maintain sufficient capture margin after laser and layer-registration tolerances are applied.

Symmetry

The stack-up should remain mechanically symmetrical whenever possible.

Balance these parameters around the centerline:

• Copper weight
• Build-up layer count
• Dielectric thickness
• Plane distribution
• Copper coverage
• Lamination materials

An asymmetric 2+6+1 stack is more likely to bow than a 2+6+2 structure because the resin, copper, and lamination stress differ between the two sides.

Typical finished bow and twist targets are:

• Below 0.75% for many surface-mount boards
• Tighter limits for large BGAs or automated assembly
• Panel-level process targets below the final acceptance limit

Impedance Control

HDI impedance is strongly affected by the thin build-up dielectric.

Typical targets include:

• Single-ended impedance: 50Ω
• Differential impedance: 85Ω, 90Ω, or 100Ω
• Production tolerance: ±7% to ±10%
• Build-up dielectric: 40–100 µm
• Outer-layer trace width: 60–120 µm
• Differential spacing: 75–150 µm

Copper plating can increase external trace thickness by 15–25 µm. The impedance model must therefore use finished copper thickness rather than base foil alone.

For high-speed signals:

• Route over a continuous reference plane.
• Avoid crossing plane splits.
• Keep layer transitions short.
• Place return vias beside signal transitions.
• Remove unused through-hole stubs where necessary.
• Model hatched planes separately from solid planes.

Key HDI PCB Manufacturing Steps

Laser Drilling

CO₂ lasers primarily remove resin-rich dielectric materials, while UV lasers provide finer energy control and can process copper and dielectric features depending on the laser system and stack design.

A controlled laser-drilling process includes:

1. Copper surface preparation
2. Target alignment
3. Laser parameter setup
4. Via ablation
5. Debris removal
6. Plasma or chemical cleaning
7. Via-bottom inspection

Critical controls include:

• Hole diameter: typically ±10–15 µm
• Target registration: typically ±25–40 µm
• Residual resin at the via bottom: not acceptable
• Excessive copper damage: not acceptable
• Via taper: controlled for plating access

Sequential Lamination

Sequential lamination builds the HDI layers in stages.

Typical lamination controls include:

• Temperature: approximately 170–210°C
• Pressure: material-system dependent
• Vacuum cycle to remove trapped air
• Controlled heating and cooling rate
• Resin-flow verification
• Layer-registration measurement

Every additional lamination cycle increases material movement. The factory must compensate artwork for expected dimensional change rather than assuming every layer remains at nominal size.

Via Filling and Plating

Microvias used under BGA pads are usually filled with copper.

A typical process includes:

• Electroless copper seed deposition
• Pattern or panel plating
• Pulse or reverse-pulse copper filling
• Surface copper reduction
• Planarization before the next build-up layer

Quality controls include:

• No internal voids
• Complete bottom coverage
• Controlled dimple
• No overfill bump
• Adequate copper at the via knee
• Stable fill across the production panel

The copper fill chemistry must balance via filling with surface plating. Excessive surface copper makes fine-line etching more difficult.

Fine-Line Etching

Fine-line fabrication requires control of both copper thickness and etching uniformity.

For 50–75 µm conductors, factories commonly control:

• Starting copper: 9–12 µm
• Additional plated copper: approximately 10–18 µm
• Dry-film alignment: ±15–25 µm
• Etch compensation: adjusted by layer and panel position
• Final conductor tolerance: commonly ±10–20 µm

A 50 µm design trace may be imaged wider so that lateral etching produces the required finished width.

Ultra HDI PCB

Ultra HDI Definition

Ultra HDI generally describes structures beyond conventional HDI capability. Industry descriptions commonly include one or more of these features:

• Line width below 50 µm
• Spacing below 50 µm
• Dielectric thickness below 50 µm
• Microvia diameter below 75 µm

These thresholds align with current industry discussions of ultra HDI and features beyond conventional IPC-2226 Level C capability.

Ultra HDI Processes

Ultra HDI production may use:

• Modified semi-additive processing
• Semi-additive processing
• Ultra-thin copper
• Direct imaging
• Embedded trace structures
• Very thin laser-drillable dielectrics
• Substrate-like manufacturing controls

Subtractive etching becomes difficult below 50 µm because lateral etching removes a significant percentage of the conductor width. Semi-additive methods build copper only where the conductor is needed, producing straighter sidewalls.

HDI vs. Ultra HDI

Quality Control

In-Process Verification

A controlled HDI PCB manufacturing plan should include:

• Incoming laminate inspection
• Inner-layer automated optical inspection
• Layer-registration measurement
• Laser-via inspection
• Desmear verification
• Copper-fill inspection
• Sequential-lamination alignment
• Fine-line AOI
• Controlled impedance testing
• Final electrical test

Typical production controls include:

Microsection and Reliability

Microsections should evaluate:

• Copper at the microvia bottom
• Via-knee plating
• Copper-fill voids
• Target-pad registration
• Dielectric thickness
• Buried-via plating
• Interlayer separation
• Resin recession

Reliability validation may include:

• Thermal stress
• Reflow simulation
• Thermal cycling
• Interconnect stress testing
• CAF testing
• Insulation resistance
• Impedance coupon testing

Microvia plating quality has a direct influence on thermal-cycle reliability, especially in stacked structures.

Factory Case Study

Fourteen-Layer Processor Board

A factory produced a 14-layer HDI board for a high-speed processor module.

The original design used:

• 3+8+3 stack-up
• Three-level stacked microvias
• 0.075 mm laser holes
• 0.20 mm microvia pads
• 0.075/0.075 mm line and space
• 0.20 mm finished mechanical vias
• 1.8 mm finished thickness
• 18 µm inner copper
• 35 µm finished outer copper
• 50Ω single-ended impedance
• 100Ω differential impedance
• ENIG surface finish
• 0.40 mm pitch BGA

Initial Production Problems

The first 36 panels showed:

• 7.8% stacked-microvia void defects
• Outer-layer impedance deviation up to +12%
• L2-to-L3 target misregistration of 45–60 µm
• Fine-line opens concentrated near panel edges
• Final electrical-test yield of 88.6%

The production review identified:

1. Three stacked microvias formed a high-risk continuous copper column.
2. Surface plating exceeded the planned thickness by 8–10 µm.
3. The outer-layer impedance model used base copper instead of finished copper.
4. Lamination compensation was identical for all build-up layers.
5. Edge-panel etching was faster than center-panel etching.

Corrective Actions

The revised build used:

• Staggered L2–L3 and L3–L4 microvias where routing space allowed
• Two-level stack limit beneath the densest BGA pads
• Copper-fill current profile adjusted by panel zone
• Finished outer copper reduced from approximately 43 µm to 34–36 µm
• Separate dimensional compensation for each build-up layer
• Differential trace width changed from 0.085 mm to 0.075 mm after field-solver review
• Edge-specific etch compensation of 8–12 µm
• Microsections added at panel center and four edge locations

Measured Results

Common Design Errors

Selecting the Stack-Up Too Late

Beginning layout before the HDI stack-up is approved can cause:

• Unbuildable microvia depths
• Incorrect impedance geometry
• Excessive lamination cycles
• Insufficient BGA escape channels
• Asymmetrical construction

The via strategy and stack-up should be frozen before detailed routing.

Excessive Stacked Microvias

Using three or four stacked levels on every BGA pad increases:

• Copper-fill demand
• Registration sensitivity
• Thermal-cycle risk
• Fabrication cost
• Inspection burden

Staggered structures or fewer stacked levels should be used wherever routing space permits.

Incorrect Via Aspect Ratio

A 100 µm laser via drilled through a 125 µm dielectric has an aspect ratio greater than 1:1. This increases plating difficulty at the via bottom.

A more stable structure may use:

• 75 µm hole through 60 µm dielectric
• 100 µm hole through 75–90 µm dielectric
• A larger hole when the dielectric cannot be reduced

Ignoring Finished Copper

Impedance, etching, and pad geometry must use finished copper thickness. Ignoring plated copper can produce:

• Lower-than-expected impedance
• Narrow conductor bases
• Excessive etch compensation
• Reduced spacing
• Solder-mask clearance problems

Missing Registration Allowance

A microvia pad must include tolerance for:

• Laser positioning
• Layer movement
• Imaging alignment
• Etching
• Lamination shift

A 75 µm hole on a 150 µm pad leaves only 37.5 µm radial capture before process tolerance. That geometry may be too aggressive for stable volume production.

FAQ

What is an HDI PCB?

Question: What makes a circuit board an HDI PCB?

Answer: An HDI PCB uses microvias, fine conductors, thin dielectric layers, blind or buried interconnections, and higher routing density than a conventional printed circuit board. Common structures include 1+N+1, 2+N+2, Type I, Type II, Type III, and any-layer ELIC.

What is an i+N+i stack-up?

Question: What does i+N+i mean in HDI PCB design?

Answer: The letter i represents the number of sequential build-up layers on each side of the central core, while N represents the core-layer count. A 2+6+2 board has two build-up layers on each side of a six-layer core, for a total of ten copper layers.

Are stacked or staggered microvias better?

Question: Should engineers use stacked or staggered microvias?

Answer: Stacked microvias provide the highest routing density because each via occupies the same vertical position. Staggered microvias consume more space but normally distribute stress more effectively and are easier to manufacture reliably. Stacked structures should be reserved for locations where density requires them.

What is the difference between HDI and ultra HDI?

Question: How is an ultra HDI PCB different from a standard HDI PCB?

Answer: Conventional HDI commonly uses 75–100 µm lines, 75–125 µm microvias, and 50–100 µm dielectrics. Ultra HDI moves below conventional limits, commonly using less than 50 µm line and spacing, microvias below 75 µm, or dielectrics below 50 µm. Ultra HDI frequently requires mSAP, SAP, or substrate-like fabrication methods.