KiCad PCB Design Guide

20 October 2026
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KiCad is a free, open-source electronic design automation (EDA) platform that supports schematic capture, PCB layout, electrical and design-rule checking, SPICE simulation, 3D visualization, and manufacturing-file generation. A reliable KiCad PCB design workflow starts with a correctly defined schematic, verified symbol-to-footprint assignments, manufacturable board geometry, and validated electrical clearances. Before ordering a PCB prototype, engineers should confirm copper thickness, trace width and spacing, finished hole sizes, board stack-up, impedance requirements, and fabrication outputs. KiCad can support professional development and production handoff, but the quality of the result depends on the design rules, library data, and verification process established by the engineer.

KiCad and PCB Design Fundamentals

What Is KiCad?

KiCad is an EDA suite used to create electronic schematics and printed circuit board layouts. It supports projects ranging from simple two-layer prototypes to complex multilayer designs.

Its main capabilities include:

Schematic Editor: Creates circuit diagrams using symbols, pins, nets, labels, and electrical connections.
PCB Editor: Defines board outlines, copper layers, footprints, tracks, vias, zones, and manufacturing constraints.
Electrical Rules Checker (ERC): Identifies schematic-level issues such as unconnected pins and invalid electrical connections.
Design Rules Checker (DRC): Checks PCB geometry against configured clearances, widths, drill rules, and connectivity requirements.
SPICE simulation: Supports circuit behavior analysis using compatible simulation models.
3D Viewer and raytracing: Visualizes component placement, board geometry, and selected 3D models.
Manufacturing output: Generates Gerber files, drill files, and other production documentation.

KiCad is especially useful when engineers want control over their design files without purchasing a proprietary EDA license. However, library quality, component-model availability, and manufacturing-rule setup still require engineering oversight.

Schematic Capture and PCB Layout

Schematic capture describes how components connect electrically. PCB layout determines how those connections are implemented physically.

A schematic may connect a microcontroller, a 3.3 V regulator, a sensor, and decoupling capacitors correctly, yet the PCB can still fail if power traces are too narrow, return paths are interrupted, or component footprints are incorrect.

The design process should distinguish three types of correctness:

Logical correctness: Components and nets match the circuit requirements.
Physical correctness: Footprints, dimensions, clearances, and placement match the real components and enclosure.
Manufacturing correctness: The selected board construction and exported files satisfy the fabricator's capabilities.

For example, a 100 MHz signal does not automatically require a particular trace width. Its impedance depends on copper geometry, dielectric thickness, material properties, and reference-plane arrangement. Controlled-impedance routing must therefore use a stack-up agreed with the PCB fabricator.

Main KiCad Design Features

Integrated SPICE Simulation

KiCad supports simulation workflows for compatible analog and mixed-signal circuits. Engineers can examine operating points, transient behavior, and frequency response where suitable models are available.

Simulation is useful for checking regulator stability, filter response, transistor switching, and amplifier behavior before building a prototype. It does not replace bench testing because model accuracy, parasitic effects, component tolerances, and PCB layout can change real-world behavior.

3D Viewer and Raytracer

The 3D Viewer helps engineers review board geometry and component placement. Available 3D models can reveal connector orientation problems, component collisions, and enclosure interference.

Raytracing improves rendered visualization, but it is not a substitute for mechanical validation. Verify critical dimensions against component datasheets and enclosure drawings rather than relying only on visual appearance.

Manufacturing Output

KiCad can generate Gerber layers, drill files, board outlines, and other fabrication data. The manufacturing package should match the fabricator's requested format and include the relevant stack-up, finish, tolerances, and special process notes.

A clean 3D model does not prove that a board is manufacturable. Fabrication readiness must be established through DRC, file review, and a design-for-manufacturing (DFM) check.

KiCad PCB Design Guide: Step by Step

Project Setup and Libraries

Create a Project

Start a new project with a clear name and dedicated working directory. Keep the schematic, PCB layout, project settings, and custom design assets together.

A useful naming convention identifies the product, revision, and release status. For example, a project can distinguish an engineering prototype from a production release without relying on file names alone.

Before design begins, define:

Board outline and maximum dimensions.
Number of copper layers.
Nominal board thickness, such as 1.6 mm.
Copper weight, such as 35 μm outer copper.
Minimum trace width and spacing.
Minimum drill and finished-hole sizes.
Required surface finish.
Controlled-impedance nets, if applicable.

These values are project inputs, not universal defaults. The final values must match the component requirements and the selected fabricator's documented capability.

Configure Libraries

KiCad libraries contain schematic symbols, PCB footprints, and associated metadata. Symbol-to-footprint consistency is essential because the schematic symbol represents electrical function while the footprint defines physical pads and dimensions.

Before assigning a footprint:

Confirm the exact manufacturer part number.
Compare the footprint with the component datasheet.
Verify pad pitch, pad dimensions, body outline, and pin numbering.
Check polarity and pin-1 orientation.
Confirm courtyard and solder-mask geometry.
Validate the footprint in the 3D Viewer when a reliable model is available.

For a 0.5 mm-pitch integrated circuit, even a small footprint error can produce assembly defects. The manufacturer datasheet and land-pattern recommendations should take precedence over an unverified community footprint.

Schematic Capture and ERC

Place Symbols

Place components from the appropriate symbol libraries, including integrated circuits, resistors, capacitors, connectors, and power symbols.

Set meaningful reference designators and values. Confirm supply voltage, signal direction, pin types, and component variants before routing.

Wire and Label

Connect component pins with wires and use net labels to identify signals. Global labels can connect signals across sheets, while local labels help keep a single sheet readable.

Power nets and ground connections should be explicit. A visually connected wire is not sufficient evidence of correct connectivity if endpoints, labels, or junctions are misplaced.

Run Electrical Rules Check

ERC checks schematic connectivity and pin-type compatibility. It can identify unconnected pins, conflicting drivers, missing power flags, and other rule violations.

The engineer should:

Resolve all unintended ERC errors.
Review warnings individually.
Document legitimate exceptions.
Verify that every required net reaches its intended pins.
Check power and ground connections against the circuit design.

ERC does not prove circuit functionality. A schematic can pass ERC while containing incorrect component values, unsuitable ratings, or a logically wrong connection.

Footprint Assignment and Annotation

Assign Footprints

Assign a physical footprint to every component that will appear on the PCB. Confirm the package code and the component manufacturer's recommended land pattern.

For example, two components with similar electrical functions may use different package sizes, pin pitches, or thermal-pad geometries. Substituting a footprint based only on the schematic symbol can lead to assembly failure.

Review:

Pad number and pin mapping.
Pitch and package dimensions.
Thermal-pad geometry.
Solder-mask expansion.
Paste-mask openings.
Mechanical courtyard and keepout areas.

Annotate the Schematic

Annotation gives components unique reference designators, such as R1, C1, U1, and J1. Stable annotation makes the BOM, assembly drawing, and placement file easier to interpret.

Before updating the PCB, confirm that reference designators are consistent and that component values and manufacturer part numbers are complete in the BOM.

PCB Layout and Design Rules

Update the PCB

Transfer the schematic components and net connections into the PCB Editor. Place footprints within the board outline and establish the intended routing topology.

Review the ratsnest to identify remaining connections. If the schematic changes, update the PCB again and inspect any changed footprints, nets, or component positions.

Arrange Components

Place components according to signal flow, thermal requirements, and mechanical constraints.

Position connectors at the required enclosure boundaries.
Keep decoupling capacitors close to the relevant power pins.
Minimize high-current loop area.
Separate sensitive analog paths from noisy switching nodes where appropriate.
Reserve room for mounting holes, test points, and assembly access.

For a switching regulator, the input capacitor, switch node, and power return form a critical current loop. Reducing the loop area can limit parasitic inductance and electromagnetic interference.

Define the Board Edge

Create a closed board outline on the designated outline layer. Check that it contains no unintended gaps, overlapping segments, or duplicate edges.

Confirm mounting-hole positions, edge clearances, panelization requirements, and any controlled-depth milling features with the fabricator.

Set Design Rules

Configure board rules before routing. The rule set should define the minimum track width, clearance, via dimensions, hole limits, copper-to-edge spacing, and any net-specific constraints.

Representative starting values for a conventional board might include:

Minimum trace width: 0.15 mm.
Minimum trace-to-trace spacing: 0.15 mm.
Typical signal via drill: 0.30 mm.
Typical signal via diameter: 0.60 mm.
Finished board thickness: 1.6 mm.
Outer copper: 35 μm.

These values are illustrative, not guaranteed manufacturing limits. Fine-pitch, HDI, high-current, or controlled-impedance designs may require different dimensions and additional constraints.

Route Tracks and Add Ground Planes

Route Tracks

Route tracks to connect all required nets while preserving clearance and signal integrity.

A practical routing order is:

Route critical clocks, differential pairs, and high-speed interfaces.
Route power paths according to current and voltage-drop requirements.
Route sensitive analog signals.
Complete ordinary digital signals.
Review unrouted connections and optimize unnecessary detours.

For differential signals, define the required impedance and pair geometry from the actual stack-up. A 100 Ω differential target is common for several interfaces, but it is not appropriate for every differential protocol. Pair spacing, trace width, dielectric height, copper thickness, and reference-plane continuity all affect impedance.

For power routing, calculate trace width from current, allowable temperature rise, copper thickness, and acceptable voltage drop. Do not use one fixed trace width for every current level.

Add Ground Planes

Copper zones can provide low-impedance return paths, reduce loop area, and improve electromagnetic compatibility when implemented correctly.

Assign the intended ground net to the zone.
Use suitable clearances around pads and tracks.
Check thermal reliefs on through-hole pads.
Refill zones after significant routing changes.
Inspect narrow copper necks and isolated copper islands.
Preserve reference-plane continuity under high-speed signals.

A ground plane split beneath a high-speed trace can force return current to detour, increasing loop area and potentially causing noise or emissions problems.

Verification and Manufacturing Export

Run Design Rules Check

DRC evaluates the physical layout against the configured rules. Typical checks include:

Track-to-track and pad-to-track clearance.
Minimum copper width.
Via drill and annular-ring constraints.
Unconnected copper nets.
Copper-to-board-edge spacing.
Solder-mask and courtyard conflicts.
Board-outline validity.

Resolve unintended DRC violations before release. A clean DRC result means the design satisfies the active rule set; it does not guarantee that the rule set itself is adequate or that every manufacturing requirement has been captured.

Inspect in 3D

Inspect the complete board in the 3D Viewer. Compare connector orientation, component heights, mounting holes, and enclosure interfaces against mechanical drawings.

Confirm critical component heights from datasheets. If a connector is 8 mm high and the available enclosure clearance is 7 mm, the design requires a mechanical change even if all electrical checks pass.

Export Manufacturing Files

The final manufacturing package commonly includes:

Gerber copper layers.
Solder-mask and silkscreen layers.
Board outline.
NC drill files.
Stack-up and fabrication drawing.
BOM and component placement data for assembly.
Assembly drawings and special process notes.

For a four-layer board, the release should clearly identify the four copper layers and their intended order. If the design requires controlled impedance, provide the stack-up and target impedance for the fabricator's review.

Before uploading files to a prototype supplier, verify that the exported board outline, drill files, copper layers, and fabrication drawing all represent the same revision.

PCB Prototype and Manufacturing Case

Representative Four-Layer Prototype

The following is an illustrative engineering case based on common PCB production conditions, not a verified customer project.

A small sensor controller is designed in KiCad with a four-layer stack-up, a 1.6 mm finished thickness, 35 μm outer copper, and a 0.15 mm minimum trace width and spacing. The board includes a microcontroller, a 3.3 V power supply, an analog sensor input, and a USB interface.

The initial layout passes ERC but has two manufacturing and engineering issues:

The ground zone is interrupted beneath part of the USB routing.
A connector footprint uses the correct pin count but does not match the selected component's physical pitch.

The engineer checks the component datasheet, corrects the footprint, restores a continuous reference plane, and reruns DRC. The board is then reviewed in 3D and exported with Gerber, drill, BOM, and placement files.

Before assembly, the prototype fabricator checks the stack-up, drill dimensions, solder-mask openings, and board outline. The assembled boards undergo visual inspection and functional testing against the project's defined requirements.

The corrected design reduces the identified risks, but any numerical improvement in yield, signal integrity, or test performance must be based on measured results. The engineering record should preserve the original issues, corrective changes, inspection data, and final test outcome.

Choosing a PCB Prototype Supplier

Prototype suppliers differ in fabrication capabilities, assembly options, lead time, material choices, and engineering support. Select a supplier based on the actual design requirements.

Hemeixin Electronics: Evaluate its documented capabilities for the required layer count, material, impedance, and assembly scope.
JLCPCB: Review its current standard and advanced fabrication options, assembly service, material availability, and ordering rules.
PCBWay: Review its current PCB fabrication, prototype, and assembly capabilities against the design package.

These suppliers are examples for evaluation, not a ranking. Capabilities, prices, lead times, and available processes can change. Obtain a current quotation and confirm the required specifications before placing an order.

For a simple two-layer prototype, standard fabrication may be sufficient. For a controlled-impedance four-layer board, HDI structure, or specialized material, obtain confirmation that the supplier can meet the stack-up and tolerances before release.

Common KiCad Design Errors

Errors That Cause Manufacturing Problems

Incorrect footprints: A library footprint that does not match the exact component can create soldering and assembly defects. Verify package dimensions and pin mapping against the manufacturer's datasheet.

Incomplete design rules: Default rules may not match the selected fabricator's capabilities. Enter the actual clearance, width, drill, and edge-spacing requirements before routing.

Unconnected nets: A board may look complete but still contain unrouted connections. Review the ratsnest and confirm DRC connectivity.

Poor ground-plane design: Splits, narrow connections, or isolated copper can disrupt return paths. Inspect ground continuity around high-speed and sensitive analog signals.

Incorrect drill assumptions: A drill diameter in the design may refer to a tool size rather than the finished plated-hole diameter. Follow the fabricator's drill and plating conventions.

Missing manufacturing information: Gerber files alone may not define material, stack-up, impedance, surface finish, or acceptance requirements. Include the fabrication drawing and supporting data.

Incomplete assembly data: A PCB layout does not replace the BOM or centroid file. Confirm component part numbers, rotation conventions, polarity, and placement coordinates.

Unreviewed 3D geometry: Missing or inaccurate 3D models can hide mechanical conflicts. Use component datasheets and enclosure drawings to verify critical clearances.

Design Quality and Release Checklist

Before releasing a KiCad PCB prototype, complete the following checks:

ERC errors are resolved or documented.
All component footprints are verified against datasheets.
Board dimensions and outline are correct.
Track width, clearance, and via rules match the fabrication requirements.
Critical nets and ground-return paths are reviewed.
DRC violations are resolved or formally accepted.
The 3D model has been checked for mechanical conflicts.
Gerber and drill files have been exported from the final revision.
The stack-up, copper thickness, surface finish, and board thickness are documented.
BOM and component placement files match the released PCB.
Prototype inspection and functional acceptance criteria are defined.

Frequently Asked Questions

Q1. Is KiCad completely free?

Yes. KiCad is free and open-source EDA software. Users can create schematics, design PCBs, run supported simulation workflows, inspect boards in 3D, and export manufacturing files without paying for a proprietary design license. Fabrication, assembly, and some external component or simulation resources may still incur costs.

Q2. Is KiCad good for beginners?

Yes. KiCad supports the complete workflow from schematic capture to PCB manufacturing output. Beginners should start with a simple two-layer board, learn ERC and DRC, verify footprints, and order a small PCB prototype before moving to fine-pitch or multilayer designs.

Q3. Do professionals use KiCad?

Yes. Engineers and organizations use KiCad for prototypes, commercial products, and other PCB design work. Professional results depend on library control, design-rule configuration, version management, documentation, and verification rather than on software choice alone.

Q4. Is KiCad as good as Altium?

Both can support serious PCB design, but their workflows and capabilities differ. KiCad offers an open-source design environment without a proprietary license fee. Altium provides a commercial environment with its own collaboration, library-management, and design-workflow features. The better choice depends on project complexity, team processes, integration requirements, budget, and support expectations.

Conclusion

KiCad provides an end-to-end workflow for schematic capture, PCB layout, simulation, 3D review, and manufacturing-file generation. Reliable results come from accurate symbols and footprints, a complete stack-up, appropriate design rules, verified routing, and a manufacturing package that matches the released revision.

For a PCB prototype, engineers should treat ERC and DRC as essential checks rather than final proof of correctness. Datasheet verification, fabricator review, assembly inspection, and functional testing remain necessary to turn a design file into a reliable electronic product.