HDI PCB Types and Stack-up Design Guide
HDI PCB types are classified by how microvias, blind vias, buried vias, plated through holes, build-up layers, and sequential lamination are arranged inside a high density interconnect board. In engineering practice, Type I and Type II cover many compact products, Type III supports higher routing density with two or more microvia build-up layers, while Types IV, V, and VI move into passive substrates, coreless structures, and advanced alternate constructions. The correct HDI type should be selected by BGA pitch, routing density, layer count, impedance target, material behavior, via reliability, and the actual hdi pcb fabrication capability of the manufacturer.
High-Density Interconnect PCB
What Defines HDI PCB
A High-Density Interconnect PCB is a printed circuit board with higher wiring density than a conventional multilayer PCB. The density increase usually comes from laser-drilled microvias, blind vias, buried vias, via-in-pad, finer traces, thinner dielectrics, and sequential build-up construction.
IPC-2226 is the main sectional design standard for HDI printed boards and is used together with IPC-2221 for printed board design requirements. The standard establishes design considerations for HDI boards and microvia technology, including via formation, dielectric separation, and interconnection structures.
A practical hdi pcb is usually selected when the product needs:
- 0.65 mm, 0.5 mm, or 0.4 mm BGA escape routing
- Higher component density in a smaller board outline
- Shorter signal transition paths
- Lower via stubs for high-speed signals
- More routing layers without excessive board size
- Better packaging for compact medical, industrial, AI, RF, or consumer devices
Factory Capability Window
| HDI Feature | Common Production Range | Advanced Range | Engineering Purpose |
|---|---|---|---|
| Trace / space | 75/75 microns | 50/50 microns or finer | Fine-pitch routing |
| Microvia diameter | 75-125 microns | 50-75 microns | Dense layer transition |
| Build-up dielectric | 50-80 microns | 25-50 microns | Microvia reliability |
| Microvia aspect ratio | 0.6:1 to 1:1 | Keep at or below 1:1 | Plating reliability |
| Mechanical drill | 0.20-0.30 mm | 0.15-0.20 mm by review | PTH and buried vias |
| Impedance tolerance | ±10% common | ±5% by review | High-speed control |
| Copper thickness | 9-18 microns for fine lines | 35 microns for power zones | Etch and current balance |
These values are not universal promises. A good hdi pcb manufacturer must confirm copper thickness, panel size, material, layer count, solder mask, finish, and inspection plan before layout release.
The 6 IPC-HDI Stack-up Types
Type I and Type II
IPC-HDI stack-up types describe the interconnection structure, not only the layer count. In simplified production language, Type I uses microvias with plated through holes but no buried vias. Type II adds buried vias in the core while still allowing through vias. Type III uses two or more microvia layers on at least one side of the core. Types IV, V, and VI are more specialized structures involving passive substrates, coreless constructions, or alternate constructions.
| IPC-HDI Type | Simplified Structure | Typical Use | Manufacturing Risk |
|---|---|---|---|
| Type I | Microvias plus PTH, no buried vias | Entry HDI, compact electronics | Lower |
| Type II | Microvias plus buried vias and PTH | Dense BGA escape, compact modules | Medium |
| Type III | Two or more microvia layers | Advanced processors, AI, medical boards | High |
| Type IV | HDI on passive substrate | Specialized high-density products | High |
| Type V | Coreless layer-pair construction | Very thin or advanced modules | Very high |
| Type VI | Alternate coreless construction | Specialized advanced interconnects | Very high |
Type I is usually the lowest-risk HDI choice. Type II becomes useful when buried vias are needed to free inner routing channels. Type III is selected when one microvia layer cannot escape the package density.
Types IV, V, and VI
Types IV, V, and VI are less common in standard industrial hdi pcb prototype work because they require tighter process control and more specialized engineering review.
Practical use cases:
- Very thin electronics where core thickness must be reduced
- High-density modules with severe z-axis constraints
- Advanced interconnect designs that cannot use a normal laminated core
- Specialized aerospace, medical, RF, or miniaturized products
- Designs where every micron of thickness and routing density matters
For most engineering teams, the key decision is not whether the most advanced HDI type exists. The better question is whether Type I, Type II, or Type III can solve routing and reliability at lower cost.
Basic HDI Structures
Build-up and Sequential Lamination
Build-up construction adds dielectric and copper layers onto a core in controlled stages. Sequential lamination repeats lamination, laser drilling, plating, imaging, etching, and inspection for each HDI build-up layer.
Typical build-up flow:
- Fabricate the inner core.
- Drill and plate buried vias if Type II or higher requires them.
- Laminate build-up dielectric and copper foil.
- Laser drill microvias.
- Clean, plate, and sometimes fill microvias.
- Image and etch build-up copper.
- Repeat the cycle for Type III or higher.
- Apply solder mask and final finish.
- Run AOI, E-test, X-ray, microsection, and impedance testing.
Sequential lamination gives more routing freedom, but each cycle adds registration movement, material shrinkage, process time, and cost.
Common Stack-up Forms
| Stack-up Form | Example | Best Fit | Factory Note |
|---|---|---|---|
| 1+N+1 | 1+4+1, 1+6+1 | 0.65 mm BGA, compact IoT | Lower lamination risk |
| 2+N+2 | 2+4+2, 2+6+2 | 0.5 mm BGA, dense modules | More routing freedom |
| 3+N+3 | 3+4+3, 3+6+3 | Processor, AI, advanced medical | Higher inspection load |
| Any-layer HDI | Microvia access across many layers | Extreme density | Needs filled microvia control |
| ELIC | Every Layer Interconnect | Very dense BGA escape | Highest process demand |
The structure should be chosen by fanout requirement and reliability margin, not by the desire to use the most advanced label.
Key Features of HDI Design
Microvias
Microvias are laser-drilled vias used for short interlayer connections. They reduce routing blockage because they do not pass through the entire board thickness like mechanical through holes.
Microvia design controls:
| Microvia Item | Practical Target | Reason |
|---|---|---|
| Diameter | 75-125 microns | Stable laser drilling and plating |
| Advanced diameter | 50-75 microns | Higher routing density |
| Dielectric depth | 50-80 microns | Supports reliable aspect ratio |
| Aspect ratio | 0.6:1 to 1:1 | Reduces plating fatigue |
| Capture pad | 200-300 microns common | Allows registration tolerance |
| Inspection | Microsection and X-ray sampling | Finds hidden plating defects |
A microvia that is too deep for its diameter can pass electrical test but fail after reflow or thermal cycling. This is why microvia reliability must be reviewed before the design becomes a production drawing.
Blind and Buried Vias
Blind vias connect an outer layer to one or more inner layers. Buried vias connect only inner layers and do not reach the board surface. HDI designs combine these structures to free surface space and improve routing density.
| Via Type | Connection | Main Value | Main Risk |
|---|---|---|---|
| Through via | Top to bottom | Low cost and simple process | Blocks routing on all layers |
| Blind via | Outer layer to inner layer | Saves space and supports fanout | Needs registration control |
| Buried via | Inner layer to inner layer | Frees outer routing area | Adds core process steps |
| Microvia | Adjacent HDI layers | Dense routing and short path | Needs plating reliability |
| Stacked microvia | Vertical microvia stack | Highest density | Requires copper filling |
| Staggered microvia | Offset microvia layers | Better reliability margin | Uses more routing area |
Via-in-Pad and Finer Pitch
Via-in-pad places the via inside the component pad. VIPPO, or via-in-pad plated over, fills and caps the via to create a flat solderable pad.
Via-in-pad is useful when:
- BGA pitch is 0.5 mm or 0.4 mm
- Dogbone routing cannot escape inner rows
- Decoupling capacitors need short power paths
- High-speed signals need short transitions
- Board area is limited
Finer pitch usually requires 75/75 micron or 50/50 micron routing. Sub-3-mil routing can be useful under dense packages, but it must be checked against copper thickness, etch capability, solder mask registration, and AOI resolution.
Type Selection Logic
Package-Driven Choice
BGA pitch often drives HDI type selection more than total layer count.
| Design Condition | Likely HDI Type | Why |
|---|---|---|
| 0.8 mm BGA with space available | Standard PCB or Type I | Dogbone routing may work |
| 0.65 mm BGA with compact outline | Type I | One build-up layer often enough |
| 0.5 mm BGA with inner-row congestion | Type II | Buried vias and microvias improve escape |
| 0.4 mm BGA with dense memory | Type III | Multiple microvia layers support fanout |
| Very dense processor or AI module | Type III, any-layer, or ELIC | Higher vertical routing freedom |
| Thin advanced module | Type V or VI by review | Coreless construction may be required |
Cost and Yield Choice
The lowest-cost design is not always the cheapest after yield loss. A Type I board that forces long routing, weak power delivery, or impossible BGA breakout may cost more in redesign than a Type II structure chosen early.
| Decision Factor | Lower HDI Type | Higher HDI Type |
|---|---|---|
| Tooling cost | Lower | Higher |
| Lamination cycles | Fewer | More |
| Routing freedom | Lower | Higher |
| Registration risk | Lower | Higher |
| Inspection burden | Lower | Higher |
| Best use | Moderate density | Dense BGA and advanced products |
A production-ready HDI type should give enough routing space with the fewest lamination cycles and the simplest reliable via structure.
Materials and Impedance
Material Selection
HDI material selection affects lamination movement, laser drilling, copper adhesion, impedance, and thermal reliability.
Common choices:
- High-Tg FR-4 for industrial and moderate-speed HDI
- Low Dk / low Df laminate for high-speed and RF boards
- Thin build-up dielectric for microvia formation
- Low-profile copper for high-speed loss control
- Polyimide for flex and rigid-flex HDI
- ENIG, immersion silver, or OSP for surface finish
| Material Item | Common Range | Engineering Role |
|---|---|---|
| Tg | 170 C or higher for demanding products | Improves reflow margin |
| Dk | 3.0-3.8 for many high-speed laminates | Controls impedance |
| Df | Below 0.005 for high-speed designs | Reduces insertion loss |
| Copper | 9-18 microns for fine lines | Improves etch precision |
| Build-up dielectric | 25-80 microns | Controls microvia depth |
| Finish | ENIG common for fine pitch | Supports flat solderable pads |
Controlled Impedance
Controlled impedance must be planned from stackup, not corrected after routing. The hdi pcb manufacturer should confirm dielectric thickness, copper thickness, line width, reference plane, and coupon design.
Typical targets:
- 50 ohm single-ended clock or RF control
- 85 ohm differential for some PCIe designs
- 90 ohm differential for USB
- 100 ohm differential for Ethernet, LVDS, and many high-speed links
- ±10% tolerance for standard production
- ±5% only when material and process justify it
IPC-6012 covers qualification and performance requirements for rigid printed boards, including multilayer boards with or without blind and buried vias. It is often used with project class requirements to define fabrication acceptance.
Hemeixin Electronics
Company Positioning
Hemeixin Electronics can be positioned as a PCB and PCBA manufacturing partner for HDI, RF, rigid-flex, flex, and multilayer PCB projects. Public company information describes its work in quick-turn PCB fabrication, NPI prototyping, multilayer PCB fabrication, and HDI any-layer printed circuit boards using laser-drilled microvias.
For an HDI PCB types article, Hemeixin should be introduced from an engineering capability angle rather than a sales angle. The practical value is whether the factory can help engineers match the HDI type to the real project condition.
Engineering review points:
- Whether Type I is enough for the package pitch
- Whether Type II is required for buried via routing
- Whether Type III or any-layer HDI is justified
- Whether the microvia diameter matches dielectric depth
- Whether via-in-pad requires filling and cap plating
- Whether impedance coupons match real routing layers
- Whether flex or rigid-flex HDI requires bend-zone review
- Whether the prototype stackup can transfer into production
Capability Fit
Hemeixin’s public capability information includes laser-drilled microvias, via-in-pad, RF and microwave boards, heavy copper, cavity PCB boards, multilayer fabrication, and boards up to 58 layers. Another Hemeixin page describes HDI flex circuits using vias as small as 50 microns and 8-micron copper for higher density in small packages.
For engineers, these points should be translated into project questions:
- Does the board need 50/50 micron routing or only 75/75 micron?
- Is the BGA pitch 0.65 mm, 0.5 mm, or 0.4 mm?
- Does the stackup need 1, 2, or 3 build-up layers?
- Are stacked microvias required, or can staggered vias improve yield?
- Can the selected material survive the lamination cycle?
- Is X-ray required for via-in-pad and filled microvias?
Quality Control by HDI Type
Inspection Plan
HDI quality control should increase as the HDI type becomes more complex.
| HDI Type | Required Inspection Focus | Production Reason |
|---|---|---|
| Type I | Laser microvias, annular ring, E-test | Basic HDI reliability |
| Type II | Buried vias, registration, microvia alignment | Core and build-up interaction |
| Type III | Stacked or staggered microvias, microsection | Multi-build-up reliability |
| Type IV | Substrate and build-up interface | Specialized construction control |
| Type V | Coreless layer pair stability | Thin structure reliability |
| Type VI | Alternate advanced construction | Project-specific validation |
Quality checks should include:
- Inner-layer AOI
- Lamination registration measurement
- Laser drill inspection
- Copper plating thickness check
- Microsection for microvias and buried vias
- X-ray for filled and stacked vias
- 100% electrical test
- Impedance coupon testing
- Solder mask registration review
- Warpage measurement after thermal simulation
Acceptance Criteria
Acceptance criteria should be written before quotation.
Define:
- IPC class
- Microvia diameter and aspect ratio
- Minimum annular ring
- Via fill type
- VIPPO dimple limit
- Controlled impedance tolerance
- Final finish
- Board thickness tolerance
- Coupon location
- Cross-section frequency
- X-ray sampling plan
A drawing that only says “HDI PCB” is not enough. The factory needs the HDI type, via map, stackup, material, impedance, and inspection requirements.
Two Key Comparisons
Type I vs Type II
| Item | Type I HDI | Type II HDI |
|---|---|---|
| Buried vias | Not used | Used in core |
| Cost | Lower | Higher |
| Routing density | Moderate | Higher |
| Best BGA fit | 0.65 mm, some 0.5 mm | Dense 0.5 mm |
| Process risk | Lower | Medium |
| Main benefit | Simple HDI entry point | Better internal routing freedom |
Type III vs Any-Layer HDI
| Item | Type III HDI | Any-Layer HDI |
|---|---|---|
| Build-up layers | Two or more microvia layers | Microvia access across many layers |
| Routing freedom | High | Very high |
| Cost | High | Very high |
| Inspection | Microsection and X-ray sampling | Heavy microsection and X-ray control |
| Best use | Dense processors and compact modules | Extreme BGA and miniaturized devices |
| Main risk | Lamination and via reliability | Filled microvia stack reliability |
Real Factory Case
Project Background
An industrial handheld diagnostic device used a 0.5 mm BGA processor, LPDDR memory, USB, MIPI display output, battery charging circuit, and a board-to-board connector. The first concept used an 8-layer standard PCB with through vias only.
| Item | Original Concept | Final HDI Choice |
|---|---|---|
| Board type | Standard multilayer PCB | Type II HDI PCB |
| Layer count | 8 layers | 10 layers |
| Stackup | Standard through-via | 2+6+2 |
| BGA pitch | 0.5 mm | 0.5 mm |
| Trace / space | 100/100 microns | 75/75 microns, 50/50 microns local |
| Via type | 0.20 mm through vias | 90 micron microvias plus buried vias |
| Finish | ENIG | ENIG |
| Impedance | 90 ohm USB | 90 ohm USB, 100 ohm MIPI |
| Inspection | AOI and E-test | AOI, E-test, X-ray, microsection, impedance coupon |
Problem and Correction
The standard PCB concept could route only the outer BGA rows cleanly. Inner rows forced long detours, and the MIPI lines crossed reference-plane gaps near through-via escape areas. The first HDI prototype used too many stacked microvias, which increased cost and inspection concern.
Factory review changed the design:
- Type II HDI replaced the standard stackup.
- Staggered microvias replaced unnecessary stacked microvias.
- Buried vias were limited to two inner routing zones.
- MIPI routing moved to a continuous reference plane.
- Copper balance was adjusted around the battery connector.
- Impedance coupons were matched to the actual routing layers.
| Metric | First HDI Prototype | Revised Pilot |
|---|---|---|
| MIPI intermittent failures | 4/50 boards | 0/120 boards |
| Microvia inspection findings | 3 suspect sites | 0 suspect sites |
| USB impedance deviation | +8% | +2.8% |
| Local warpage | 0.48 mm | 0.22 mm |
| First-pass functional yield | 88.0% | 97.5% |
The final solution did not require Type III or any-layer HDI. Type II gave enough routing density with lower manufacturing risk.
Common Design Errors
Type Selection Errors
- Selecting Type III when Type II is enough
- Using Type I for dense 0.4 mm BGA without fanout review
- Assuming any-layer HDI automatically improves reliability
- Choosing a stackup before reviewing BGA ball map
- Ignoring buried via cost in Type II designs
- Not matching HDI type to production volume
Via Design Errors
- Exceeding microvia aspect ratio limits
- Using stacked microvias where staggered vias fit
- Calling out via-in-pad without fill and cap details
- Missing buried via layer pairs in fabrication notes
- Forgetting microsection coupons
- Mixing via structures without a lamination sequence
Fabrication Errors
- Changing material after prototype approval
- Using 35 micron copper in dense fine-line zones
- Omitting controlled impedance coupons
- Ignoring material shrinkage in sequential lamination
- Not checking copper balance
- Treating PCB and PCA validation as the same
PCB is the bare printed circuit board. PCA is the assembled circuit board with components, solder joints, firmware, inspection records, and functional test data. A bare hdi pcb can pass E-test while the PCA fails because of BGA solder defects, warpage, or high-speed margin loss.
FAQ About HDI PCB Types
Question: What are the main HDI PCB types?
Answer: The main HDI PCB types are Type I, Type II, Type III, Type IV, Type V, and Type VI. Type I uses microvias without buried vias. Type II adds buried vias. Type III uses two or more microvia layers. Types IV, V, and VI are specialized structures for passive substrates, coreless constructions, or alternate advanced HDI builds.
Question: What is the difference between Type I and Type II HDI PCB?
Answer: Type I HDI uses microvias and plated through holes but does not use buried vias. Type II HDI adds buried vias in the core, which gives more internal routing freedom. Type II costs more but supports denser BGA escape and more complex hdi circuit boards.
Question: When should engineers use Type III HDI PCB?
Answer: Engineers should use Type III HDI when the design needs two or more microvia build-up layers on at least one side of the board. It is common for dense processors, compact medical boards, AI modules, and high-speed products where Type I or Type II cannot provide enough routing density.
Question: How should engineers choose the right HDI PCB type?
Answer: Engineers should choose the HDI PCB type by BGA pitch, ball count, routing density, layer count, signal speed, power delivery, material behavior, inspection requirement, and production volume. The best type is the simplest structure that meets routing and reliability goals with stable hdi pcb fabrication yield.



