How to Calculate HDI PCB Impedance

20 June 2026
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Calculating impedance for High-Density Interconnect (HDI) boards means defining the target impedance, selecting the correct transmission-line structure, entering real manufacturing parameters, solving the trace geometry, and confirming the result with the HDI PCB manufacturer before fabrication. In practical HDI PCB work, the calculation is not only a software number. It depends on finished trace width, copper thickness, dielectric thickness, dielectric constant, trace shape after etching, reference plane continuity, solder mask effect, and impedance coupon verification after HDI PCB fabrication.

Calculating Impedance for High-Density Interconnect Boards

HDI PCB impedance calculation is required when a signal trace behaves as a transmission line. In factory review, controlled impedance is normally applied to high-speed nets such as PCIe, USB 3.x, HDMI, Ethernet, MIPI, LVDS, DDR clocks, RF feed lines, FPGA transceivers, and SerDes channels.

Common targets used in HDI circuit boards include:

50 ohm single-ended traces
90 ohm differential pairs
100 ohm differential pairs
Plus or minus 10 percent tolerance for standard controlled impedance
Plus or minus 7 percent tolerance for advanced high-speed HDI PCB fabrication
Plus or minus 5 percent tolerance only after stackup and process review

The calculation becomes more sensitive in high density interconnect products because the dielectric may be only 50 micrometer to 100 micrometer thick, trace width may be 2.5 mil to 4.5 mil, and laser microvias may sit close to controlled traces. A small etching shift of 0.3 mil can move impedance by several ohms on thin dielectric layers.

Parameters

The main impedance parameters are:

Trace Width (W)
Trace Thickness (t)
Dielectric Thickness (h)
Dielectric Constant
Trace Shape (W1 vs W2)
Reference plane distance
Solder mask thickness
Differential pair spacing
Copper roughness
Final manufacturing tolerance

A reliable calculation must use finished production values, not only CAD values. For example, a 3.8 mil designed trace may become 3.5 mil to 3.6 mil after etching, depending on copper thickness, compensation, and pattern density.

Trace Width (W)

Trace Width (W) is the most direct adjustment parameter. Wider traces reduce impedance, while narrower traces increase impedance.

Typical HDI PCB trace ranges are:

Standard HDI routing: 3/3 mil
Advanced HDI routing: 2.5/2.5 mil
High-end HDI routing: 2/2 mil after factory review
Common 50 ohm single-ended trace width: 3.5 mil to 6.0 mil
Common 100 ohm differential trace width: 3.5 mil to 5.0 mil
Local BGA neck-down: 2.5 mil to 3.0 mil

From the HDI PCB manufacturer side, trace width must stay inside an etching window. A 2.5 mil trace may be possible on 0.5 oz copper, but it becomes higher risk when the copper is 1 oz or when copper density is uneven across the panel.

Trace Thickness (t)

Trace Thickness (t) is the finished copper thickness after base copper, plating, and etching. Thicker copper lowers impedance and increases etching difficulty.

Typical copper values include:

5 oz copper: about 17 micrometer base copper
1 oz copper: about 35 micrometer base copper
Finished outer copper after plating: commonly 35 micrometer to 50 micrometer
Fine-line inner-layer copper: commonly 0.5 oz for 2.5/2.5 mil or 3/3 mil routing

For impedance calculation, the finished copper thickness must be used. If the drawing says 1 oz finished copper but the calculator uses 0.5 oz, the calculated width may be wrong.

Dielectric Thickness (h)

Dielectric Thickness (h) is the distance between the signal trace and the reference plane. Smaller h lowers the required trace width for the same impedance, which helps dense routing under fine-pitch BGAs.

Typical HDI values include:

Laser build-up dielectric: 50 micrometer to 75 micrometer
Fine-line impedance dielectric: 75 micrometer to 100 micrometer
Standard internal dielectric: 100 micrometer to 150 micrometer
Finished board thickness: 0.8 mm to 2.4 mm

A 10 micrometer press thickness shift can affect impedance on very thin HDI layers. This is why HDI PCB fabrication must lock the stackup before final routing.

Dielectric Constant

Dielectric Constant, or Dk, controls how fast the signal travels through the dielectric and how much capacitance forms around the trace. Higher Dk lowers impedance; lower Dk raises impedance.

Common material ranges include:

Standard FR-4 Dk: 4.0 to 4.5
Mid-loss material Dk: 3.6 to 4.0
Low-loss material Dk: 3.2 to 3.8
Standard FR-4 Df: 0.015 to 0.020
Low-loss material Df: 0.003 to 0.010
High-Tg HDI material: 170 degrees Celsius to 200 degrees Celsius

For an HDI PCB prototype running below several Gbps, standard high-Tg FR-4 may be acceptable. For 25 Gbps, 56 Gbps, or 112 Gbps channels, low-loss material and smoother copper must be reviewed together with impedance.

Trace Shape (W1 vs W2)

Trace Shape (W1 vs W2) matters because etched copper is not a perfect rectangle. The trace usually has a trapezoidal profile.

In production:

W1 is often the top trace width
W2 is often the bottom trace width
The average width is used by many field solvers
Etch factor changes with copper thickness
3 mil to 0.8 mil compensation may be applied in CAM
Fine-line traces below 3 mil are more sensitive to over-etching

A factory calculation based only on nominal CAD width can be inaccurate. For high density interconnect designs, the CAM engineer should calculate impedance using finished trace geometry after etching compensation.

HDI PCB Configurations

HDI PCB Configurations define the transmission-line model. The same width can create different impedance depending on whether the trace is on the outer layer, inner layer, or surrounded by ground copper.

Common configurations include:

Surface Microstrip
Stripline
Coplanar Waveguide
Coated microstrip with solder mask
Differential microstrip
Differential stripline

The selected structure must match the real layer stackup. A 4.0 mil trace on L1 referencing L2 does not equal a 4.0 mil trace on L3 between L2 and L4.

Surface Microstrip

Surface Microstrip is an outer-layer trace over a reference plane. It is common for RF lines, clocks, and short high-speed connections.

Typical values:

Reference plane: usually the next inner ground layer
Dielectric height: 50 micrometer to 150 micrometer
Solder mask thickness: about 10 micrometer to 25 micrometer
Common impedance: 50 ohm single-ended or 90 ohm differential

Surface microstrip is easy to inspect and adjust, but it is more exposed to solder mask variation and environmental effects than internal stripline. For a 50 ohm trace, solder mask can reduce impedance by several ohms, so coated microstrip must be modeled when tolerance is tight.

Stripline

Stripline is an internal trace between two reference planes. It provides better shielding and more stable impedance than surface microstrip.

Typical values:

Inner signal layer between two planes
Dielectric distance to each plane: 75 micrometer to 150 micrometer
Common impedance: 50 ohm single-ended or 100 ohm differential
Copper thickness: usually 0.5 oz or 1 oz inner copper

Stripline is preferred for longer high-speed routes because the field is contained between planes. The tradeoff is that inner-layer defects must be caught by inner-layer AOI before lamination.

Coplanar Waveguide

Coplanar Waveguide uses ground copper beside the signal trace and a reference plane below. It is often used for RF or high-speed outer-layer routing when field confinement is needed.

Key parameters include:

Signal trace width
Gap to coplanar ground
Dielectric height to lower reference plane
Solder mask condition
Ground via spacing
Copper thickness

Typical coplanar ground clearance may be 5 mil to 8 mil, depending on impedance and fabrication capability. Ground stitching vias may be placed every 1 mm to 2 mm along RF routes to stabilize the return path.

Step-by-Step Calculation Process

A practical HDI PCB impedance calculation flow includes:

Define signal type and target impedance.
Select the stackup and reference plane.
Choose microstrip, stripline, or coplanar waveguide.
Enter finished copper thickness.
Enter dielectric thickness after lamination.
Enter material Dk at the operating frequency.
Add solder mask for outer-layer impedance.
Enter differential spacing when needed.
Run a field solver.
Check whether the result is manufacturable.
Send the stackup to the HDI PCB manufacturer.
Confirm coupon design and TDR test requirements.

This process prevents a common problem: the design tool produces a width that works electrically but cannot be repeated during HDI PCB fabrication.

Choose Your Target Impedance

Choose your target impedance based on the interface specification, not by guessing.

Common targets are:

50 ohm single-ended for RF, clocks, and many high-speed single-ended nets
90 ohm differential for USB and some MIPI or LVDS applications
100 ohm differential for PCIe, Ethernet, HDMI, and many SerDes channels

A tolerance of plus or minus 10 percent is common for many digital designs. Plus or minus 7 percent is used when signal margin is tighter. Plus or minus 5 percent should be used only when the HDI PCB manufacturer confirms that stackup, material, etching, and testing can support it.

Consult Your Fabricator

Consult your fabricator before final routing. The factory has actual data for laminate availability, prepreg press thickness, copper thickness, laser drilling capability, etching compensation, and impedance coupon design.

The fabricator should confirm:

Available material Dk and Df
Pressed dielectric thickness
Finished copper thickness
Minimum line and space
Laser microvia diameter
Microvia pad diameter
Sequential lamination structure
Impedance tolerance
Coupon structure
TDR measurement method

For example, if a field solver gives 3.1 mil for a 50 ohm stripline but the stable production minimum is 3.5 mil, the better solution is to adjust dielectric thickness rather than force the trace width.

Use a Field Solver

Use a field solver for final impedance geometry. Online calculators can provide early estimates, but HDI circuit boards often require more accurate modeling.

A field solver should include:

Finished trace width
Finished copper thickness
Dielectric height
Dk value
Differential pair spacing
Solder mask
Copper shape
Coplanar ground gap
Reference plane location

Field solver output must be checked against factory capability. A calculated 2.2 mil trace may meet impedance, but it may create yield loss if the HDI PCB fabrication process is built around 3/3 mil production.

Adjust Parameters

Adjust parameters in a controlled order. Do not change everything at once.

Practical adjustment sequence:

Change trace width first.
Adjust pair spacing for differential impedance.
Modify dielectric thickness if width is not manufacturable.
Confirm copper thickness.
Review material Dk.
Add or remove solder mask in the model.
Check reference plane continuity.
Recalculate after CAM compensation.

Factory experience shows that dielectric thickness adjustment is often cleaner than pushing trace width below the stable etching limit.

Design Practices

Design Practices for HDI PCB impedance are based on field control and manufacturability.

Effective practices include:

Lock the stackup before routing
Use ground as the main reference plane
Keep controlled traces away from plane splits
Keep differential pairs symmetrical
Use short neck-down only inside BGA escape zones
Avoid unnecessary 2/2 mil routing
Use 0.075 mm microvias only when density requires them
Keep impedance coupons matched to real routed layers
Avoid changing material after routing

These practices reduce rework during CAM review and improve the chance that the HDI PCB prototype can move into production without redesign.

Keep References Adjacent

Keep references adjacent to controlled traces. A controlled impedance trace needs a continuous return path close to the signal path.

Factory rules include:

L1 signal should reference L2 ground
L3 signal should reference L2 or L4 ground
High-speed layers should sit next to continuous ground planes
Stitching vias should be placed within 1 mm to 2 mm of layer transitions
Differential via transitions should be symmetrical
High-speed traces should not cross split planes

A trace can pass theoretical width calculation but fail in the real channel if the return path is broken.

Avoid Discontinuities

Avoid discontinuities because impedance changes cause reflection, eye closure, and EMI.

Common discontinuities include:

Long BGA neck-down traces
Via stubs longer than 0.25 mm to 0.50 mm on high-speed channels
Plane splits under controlled traces
Large anti-pad fields
Asymmetrical differential pair vias
Sudden width changes
Connector breakout voids
Uncontrolled test pads on high-speed routes

For high-speed HDI PCB fabrication, back drilling, blind vias, or shorter via transitions may be required when via stubs affect signal integrity.

Differentiate Widths

Differentiate widths by layer and structure. One impedance value does not mean one trace width across the entire board.

Structure	Typical Use	Example Geometry	Main Risk
Surface microstrip	Outer-layer routing	4.5 mil over 75 micrometer dielectric	Solder mask shifts impedance
Stripline	Internal high-speed routing	3.8 mil between two planes	Lamination thickness variation
Coplanar waveguide	RF or outer high-speed route	5.0 mil trace with 6.0 mil ground gap	Ground via spacing affects return path

A 50 ohm trace on L1 may require 4.5 mil, while the same 50 ohm target on L3 may require 3.6 mil. The fabrication drawing must list each structure separately.

Specifying for Manufacturing

Specifying for Manufacturing means giving the HDI PCB manufacturer enough information to build and verify the impedance.

The fabrication drawing should include:

Target impedance
Tolerance
Layer number
Trace width
Differential spacing
Reference plane
Material Dk
Dielectric thickness
Finished copper thickness
Solder mask condition
Coupon requirement
TDR test requirement
IPC class
Controlled stackup requirement

A strong drawing does not only say “controlled impedance required.” It defines exactly which traces are controlled, how they are built, and how the factory must verify them.

Quality Control for Impedance

Quality control must connect calculation with production measurement.

A practical HDI PCB quality flow includes:

CAM impedance review before production
Stackup confirmation before lamination
Inner-layer AOI for fine-line inspection
Copper thickness measurement
Lamination thickness check
Microsection for plating and dielectric verification
Impedance coupon fabrication on the production panel
TDR testing after fabrication
Final electrical test by netlist
Impedance report with measured values

Acceptance values should be stated clearly. A 100 ohm differential pair with plus or minus 10 percent tolerance is acceptable from 90 ohm to 110 ohm. A plus or minus 5 percent requirement narrows the window to 95 ohm to 105 ohm and increases process risk.

Key Comparison Tables

Item	Calculator Estimate	Field Solver
Best stage	Early stackup planning	Final impedance verification
Inputs	Basic W, h, t, Dk	Finished geometry, solder mask, copper shape
Accuracy	Moderate	Higher
HDI use	Quick feasibility check	Production release
Factory value	Finds rough width	Confirms manufacturable geometry

Requirement	Controlled Stackup	Controlled Impedance
Main control	Physical layer build	Electrical ohm value
Data required	Copper, dielectric, material	Target, tolerance, coupon
Verification	Thickness and construction check	TDR measurement
Main risk	Wrong layer structure	Signal reflection
Best result	Process stability	Signal integrity

Real Factory Case

A 12-layer 2-step HDI PCB prototype was reviewed for a high-speed FPGA module. The design used 0.5 mm BGA, 100 ohm differential pairs, 50 ohm clocks, buried vias, and via-in-pad plated over pads.

Original build data:

Layer count: 12 layers
HDI structure: 2+N+2
Board thickness: 1.6 mm
Material: high-Tg 180 degrees Celsius class
Minimum trace and spacing: 3/3 mil
Local BGA escape: 2.5/2.5 mil
Laser microvia: 0.10 mm
Microvia pad: 0.25 mm
Mechanical via: 0.20 mm
Surface finish: ENIG
Controlled impedance: 50 ohm single-ended and 100 ohm differential
Original tolerance: plus or minus 5 percent

CAM review found four problems:

L3 differential pairs were 3.0 mil width and 4.0 mil spacing, calculating near 92 ohm instead of 100 ohm
L3 dielectric was 75 micrometer, too thin for the required geometry
Several pairs crossed a reference plane opening near a power island
Coupon structure did not match the actual routed stripline layer

Corrective actions:

L3 dielectric increased from 75 micrometer to 90 micrometer
Differential width changed from 3.0 mil to 3.5 mil
Differential spacing changed from 4.0 mil to 5.5 mil
Ground reference was restored under the SerDes breakout
Stitching vias were added within 1.5 mm of layer transitions
Impedance tolerance was revised from plus or minus 5 percent to plus or minus 7 percent
Coupon structure was rebuilt to match actual L3 geometry

Measured result after first article:

100 ohm differential coupons measured from 96.8 ohm to 103.5 ohm
50 ohm single-ended coupons measured from 48.7 ohm to 51.9 ohm
Microsection confirmed stable copper plating in laser vias
AOI confirmed no over-etched fine-line defects
Electrical test passed by netlist
No layout redesign was required after prototype verification

This case shows that HDI PCB impedance calculation must be connected to stackup, CAM compensation, reference planes, and final TDR measurement.

Common Design Errors from Production

Using CAD width as finished width
Finished trace width changes after etching and compensation.
Applying one width to all layers
Surface microstrip, stripline, and coplanar waveguide require different widths.
Ignoring solder mask
Outer-layer coated microstrip impedance changes when solder mask is added.
Selecting plus or minus 5 percent by default
Tight tolerance increases rejection risk when the interface does not require it.
Routing over split planes
The trace width may be correct, but the return path is broken.
Extending BGA neck-down too far
A 2.5 mil breakout trace should not continue for 30 mm if the main impedance width is 4.2 mil.
Changing laminate after routing
Different Dk or dielectric thickness invalidates the impedance calculation.
Missing coupon requirements
Without a matched coupon, TDR testing cannot verify the actual controlled structure.

FAQ

Question: How do you calculate impedance for HDI boards?

Answer: Calculate impedance for HDI boards by selecting the target impedance, choosing the transmission-line structure, entering finished trace width, copper thickness, dielectric thickness, Dk, solder mask, and differential spacing into a field solver, then confirming the result with the HDI PCB manufacturer and verifying it through TDR coupons after fabrication.

Question: What parameters affect HDI PCB impedance the most?

Answer: The strongest parameters are trace width, dielectric thickness, copper thickness, dielectric constant, trace shape after etching, differential spacing, solder mask, and reference plane continuity. In thin HDI dielectric layers, a 0.3 mil trace width shift or a 10 micrometer dielectric shift can change measured impedance.

Question: Is a field solver necessary for HDI PCB fabrication?

Answer: A field solver is necessary for final HDI PCB fabrication when the design uses thin dielectric, differential pairs, coated microstrip, coplanar waveguide, asymmetric stripline, tight tolerance, or high-speed SerDes channels. Simple calculators are useful for early estimates but not enough for production release.

Question: What should be specified for controlled impedance manufacturing?

Answer: The fabrication drawing should specify target impedance, tolerance, layer, trace width, pair spacing, reference plane, dielectric thickness, Dk, finished copper thickness, solder mask condition, coupon requirement, TDR test requirement, IPC class, and controlled stackup requirement.