Microvia Design for Manufacturing (DFM) Checklist

1. Core Microvia Geometry & Aspect Ratio

•  Finished microvia diameter: 20–150µm (0.8–6 mils) (IPC-2226 definition)
•  Aspect ratio (depth:diameter) ≤1:1 (preferred 0.5:1–0.8:1 for plating uniformity)
•  Hole depth matches dielectric thickness (50–100µm for HDI layers)
•  Taper angle of laser-drilled vias: 10–15° (ensures plating coverage)

2. Pad & Annular Ring Requirements

•  Target land size: 229–406µm (9–16 mils) (IPC-2226 Level A/C)
•  Annular ring: ≥25µm (1 mil) for Level A; ≥15µm (0.6 mil) for Level C
•  Capture land size: ≥152µm (6 mils) (Level A); ≥76µm (3 mils) (Level C)
•  No "necked" annular rings (minimum 10µm at thinnest point)

3. Via-in-Pad (VIP) Specific Checks

•  VIP diameter ≤75% of pad diameter (e.g., 75µm via for 100µm pad)
•  VIPs are fully filled (copper for high-reliability; conductive paste for cost-sensitive)
•  Filled VIPs planarized to ±5µm of pad surface (prevents solder pooling)
•  Solder mask open over entire pad (avoids solder mask entrapment)
•  No VIPs in thermal pad centers (use staggered thermal vias instead)

4. Stacked/Staggered Microvia Rules

•  Stacked vias: Max 2 vias per stack (IPC reliability guideline)
•  Internal stacked vias are filled + capped (prevents plating voids)
•  Staggered vias: ≥100µm (4 mils) horizontal offset between adjacent layers
•  Stacked via alignment tolerance: ±10µm (0.4 mils) (ensures electrical continuity)

5. Clearance & Spacing

•  Microvia-to-microvia (center-to-center): ≥50µm (2 mils) Level A; ≥30µm (1.2 mils) Level C
•  Microvia-to-trace: ≥25µm (1 mil) Level A; ≥15µm (0.6 mils) Level C
•  Microvia-to-through-hole via: ≥100µm (4 mils)
•  Microvia-to-component pad: ≥50µm (2 mils) (prevents solder wicking)

6. Material & Plating Compliance

•  Dielectrics: IPC-4104 compliant (e.g., high-Tg FR-4, Rogers 4350 for RF)
•  Copper plating thickness: ≥10µm (Level A/B); ≥15µm (Level C) (barrel & pad)
•  Plating uniformity: ≤20% variation across via barrel (cross-sectional check)
•  Filling material compatibility with plating (copper fill = pulsed electrolytic plating)

7. Fabrication Process Compatibility

•  Laser drillability: Material supports target via diameter (UV-YAG for FR-4; CO₂ for polyimide)
•  Desmearing compatibility (plasma for ≤50µm vias; chemical for ≥50µm)
•  No overlapping drill patterns (avoids dielectric damage)
•  Fiducial marks included (≥3 per PCB for layer alignment)

8. Reliability & Thermal Checks

•  Thermal vias (if used): Density ≥100 vias/cm² near hotspots (e.g., QFP centers)
•  No microvias within 50µm of PCB edges (prevents delamination)
•  CTE match: Dielectric CTE (13–17 ppm/°C) aligned with copper (16.5 ppm/°C)
•  Void volume in filled vias: ≤5% (IPC-6016 requirement)

9. Documentation & Fabrication Files

•  Gerber files label microvia types (blind/buried/VIP/stacked)
•  Drill file specifies laser drill parameters (wavelength, speed)
•  Stackup report includes HDI layer thicknesses & material IDs
•  Cross-sectional diagram of stacked/staggered vias provided
•  IPC class (A/B/C) and reliability requirements (e.g., 1,000 thermal cycles) noted

10. Final DFM Validation

•  ECAD DRC run (constraints: IPC-2226 Level A/C)
•  Fabricator pre-approval (checks for laser drilling limits)
•  Test vehicle included for prototype validation (microvia sampling)