Multi-Step Cavity PCB: Design and Manufacturing

11 November 2026
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What Is a Multi-Step Cavity PCB?

A multi-step cavity PCB is a multilayer printed circuit board containing two or more recessed platforms at different controlled Z-axis depths. These platforms accommodate semiconductor dies, wire bonding pads, embedded components, thermal structures, or miniature electronic modules. Unlike a conventional single-depth cavity, the stepped construction places electrical connections and components at different elevations within the same board. Manufacturing requires controlled-depth milling, precise layer registration, reliable cavity-floor preparation, and coordinated assembly. The main engineering advantage is reduced package height and shorter interconnections without requiring a separate substrate for every component.

A multi-step cavity PCB can also integrate HDI PCB features, including blind vias, buried vias, and fine-pitch routing. However, cavity machining removes structural material, so the design must balance electrical density against remaining board thickness, mechanical strength, and dimensional stability.

Structure and Manufacturing

Multi-Depth Platforms

A typical construction contains three functional elevations:

Upper platform: Surface-mount components and external connectors.
Intermediate shelf: Wire bonding pads or secondary die connections.
Lower cavity floor: Semiconductor die attachment or recessed component mounting.

For a 2.40 mm-thick eight-layer board, example cavity depths measured from the top surface might be 0.50 mm, 1.00 mm, and 1.45 mm.

The remaining thickness below the deepest pocket would be 0.95 mm.

These dimensions must be coordinated with copper-layer locations. A milling operation cannot cut through functional conductors simply because the mechanical depth is achievable.

IPC Cavity Classifications

IPC standards provide design, performance, and acceptance requirements for printed boards, but there is no universally applicable IPC classification that assigns all multi-step cavities to a fixed set of named depth categories.

Manufacturers commonly describe cavity constructions by their fabrication method and function:

Cavity construction	Manufacturing approach	Typical application
Controlled-depth cavity	Mechanical milling	Recessed components
Sequentially laminated cavity	Preformed layer openings	Embedded modules
Copper-bottom cavity	Controlled exposure of copper	Die attachment
Multi-step cavity	Multiple controlled elevations	Multi-tier wire bonding
HDI cavity construction	Cavity with microvia routing	Dense electronic packages

IPC-2221 provides general printed-board design principles, while IPC-6012 establishes qualification and performance requirements for rigid printed boards. Project-specific cavity tolerances must be defined in the procurement documentation.

Primary Benefits

Multi-depth architecture provides several advantages:

Higher I/O density: Separate bonding shelves distribute connection pads around a semiconductor die.
Reduced package height: A 0.60 mm-thick die recessed by 0.50 mm projects only 0.10 mm above its mounting reference, before adhesive and encapsulation.
Shorter interconnections: Properly positioned shelves can reduce wire length and associated parasitic inductance.
Mechanical integration: A recessed component can be protected within the board outline.
Thermal integration: A metal-backed or thermally connected floor may provide a heat-transfer path when designed and tested appropriately.

A cavity does not inherently improve thermal performance. An FR4 floor with low thermal conductivity may remain a significant thermal bottleneck.

Controlled-Depth Routing

Controlled-depth routing uses a calibrated cutting tool to remove selected laminate material without damaging the underlying structure.

Important variables include:

Spindle runout and tool wear.
Router diameter and corner geometry.
Board support and vacuum fixture stability.
Laminate thickness variation.
Z-axis calibration and surface mapping.
Remaining copper and dielectric thickness.

A representative cavity may require a depth tolerance of ±0.075 mm. More demanding designs may target ±0.05 mm after process qualification.

These values are proposed fabrication specifications, not universal factory capabilities.

Cavity Tolerance and Flatness

Feature	Example design requirement
Cavity depth	±0.075 mm
Tight depth requirement	±0.050 mm
X/Y pocket dimensions	±0.100 mm
Internal corner radius	At least 0.50 mm
Minimum residual web	0.40 mm
Local floor flatness	0.050 mm across 15 mm
Board bow/twist	Per applicable IPC class and assembly requirements

A 1.0 mm diameter router normally produces an internal corner radius of approximately 0.50 mm.

Smaller corners require a smaller cutter, another fabrication method, or mechanical relief.

The minimum residual web depends on the laminate construction, unsupported span, handling requirements, and adjacent copper layers.

PCB Bow and Twist Standards

For conventional rigid boards, IPC-6012 commonly specifies maximum bow and twist of 0.75% for boards with surface-mount components and 1.5% for other boards, subject to the applicable revision and procurement requirements.

These are global board acceptance criteria, not cavity-floor flatness specifications.

For a 100 mm board dimension, 0.75% corresponds to 0.75 mm when evaluated using the applicable measurement definition.

A wire-bonding floor requiring 0.05 mm flatness therefore needs its own local specification.

Asymmetry and Stress

Deep pockets create uneven laminate thickness and stiffness.

An asymmetric copper distribution can increase distortion during lamination, machining, or thermal processing.

A cavity positioned close to one board edge may require additional panel support.

Copper balance should be evaluated across the complete panel, not only around the cavity opening.

DFM Guidelines for Cavities

Use One Z-Datum

All cavity depths should reference one clearly defined controlling datum, usually the finished top surface.

If one shelf is dimensioned from the top surface and another from the cavity floor, tolerance accumulation becomes difficult to control.

For example:

Datum A: Finished top surface.
Shelf 1 depth: 0.50 ±0.05 mm.
Shelf 2 depth: 1.00 ±0.05 mm.
Floor depth: 1.45 ±0.05 mm.

The manufacturing drawing must specify whether these dimensions apply before or after surface finishing.

Adaptive Surface Mapping

For tight-depth cavities, measure the panel surface at multiple locations before milling.

Adaptive surface mapping adjusts tool depth relative to the measured board surface.

This can compensate for panel height variation, although it cannot eliminate internal laminate thickness variation.

Balance Remaining Copper

Maintain balanced copper distribution where possible.

Large copper removal near only one side of the stackup can contribute to warpage and local mechanical instability.

Copper Planes as Depth Stops

An internal copper plane can serve as a depth-reference feature or exposed cavity floor in a specially engineered construction.

However, ordinary 18 or 35 μm copper is not a mechanically robust milling stop.

If copper is used as a stop or exposed floor, the process must qualify tool control, copper thickness, electrical isolation, and surface damage limits.

Copper-to-Wall Clearances

A preliminary design may reserve 0.25–0.50 mm between functional copper and a routed cavity wall.

The required clearance depends on routing tolerance, layer registration, and conductor exposure.

Floor and Wall Conditions

Specify whether the cavity requires:

Exposed copper or dielectric.
Plated or unplated walls.
Adhesive-compatible surface roughness.
Defined contamination limits.
Controlled burrs and resin smear.

A wire-bonding cavity also requires protection against debris that could contaminate bond pads.

Cross-Section Documentation

A complete drawing should identify:

Every cavity elevation and unique feature ID.
X/Y dimensions and corner radii.
Z-depths from the controlling datum.
Copper and dielectric layers intersected.
Surface finish and bonding requirements.
Local floor flatness and remaining web thickness.
Inspection method and acceptance criteria.

The CAD stackup must match the manufacturing cross-section. A two-dimensional pocket outline alone is insufficient for a multi-tier cavity.

Wire Bonding and Production

Multi-Step Cavity Wire Bonding

A multi-step cavity PCB with wire bonding pads places semiconductor dies and their electrical terminals at different elevations.

This arrangement is useful when a die has a large number of connections or when its bonding perimeter cannot accommodate all required wires on one level.

Multi-Tier Connection Architecture

Die Attach Floor

The lowest platform supports the semiconductor die.

A representative assembly may use a 5 × 5 mm die attached to a 7 × 7 mm recessed floor with a qualified adhesive.

The adhesive thickness, die placement tolerance, and floor planarity influence the final bonding height.

Stepped Bond Shelves

Intermediate shelves carry plated bonding pads.

A preliminary design may use:

Bond pad width: 125 μm.
Bond pad length: 250 μm.
Pad pitch: 200 μm.
Shelf width: 0.80 mm.
Minimum cavity-wall clearance: 0.30 mm.

These dimensions are illustrative. Actual pad geometry depends on wire diameter, bonding equipment, pad metallurgy, placement accuracy, and the chosen bonding process.

Multi-Tier Wire Bonding

Wire bonds connect die terminals to pads on the surrounding shelves.

A representative fine-wire process may use 18–25 μm gold wire, although aluminum and copper wire technologies are also available.

Wire diameter, bond type, and loop profile must be qualified together.

Shorter wires can reduce parasitic inductance, but the electrical improvement depends on wire geometry and return-current paths.

Loop Height Clearance

The design must account for the maximum wire-loop envelope.

For example, if a qualified bonding process produces a maximum loop height of 250 μm above the highest bond reference, the enclosure must provide additional clearance for placement variation and encapsulation.

A nominal 300 μm lid clearance may be insufficient once all tolerances are included.

Surface Plating and Bondability

Wire bonding requires a suitable metallic bonding surface.

Possible finishes include electrolytic soft gold over nickel or other qualified wire-bondable metallization systems.

Conventional ENIG used for soldering must not automatically be treated as suitable for every gold-wire bonding process.

Surface qualification should evaluate:

Gold thickness and purity.
Nickel barrier characteristics.
Pad contamination.
Bond pull or shear performance.
Metallurgical compatibility.
Thermal aging effects.

The approved finish must be specified separately from ordinary SMT solderability requirements.

Glob-Top Encapsulation

Glob-top material protects the die and bond wires from mechanical contact and environmental exposure.

The encapsulant must be compatible with the die, bond metallurgy, cavity geometry, and operating temperature.

Dispensing volume and curing shrinkage require control because excessive encapsulation stress can damage wires or shift their loops.

For assemblies requiring a lid, the designer must also verify encapsulant height and cavity-wall clearance.

Multi-Tier Architecture Comparison

Design feature	Single-level cavity	Multi-step cavity
Bonding elevations	One	Two or more
Pad distribution	Single perimeter	Multiple shelves
Mechanical complexity	Lower	Higher
Wire-loop planning	Simpler	Multiple elevations
Depth inspection	One primary floor	Every shelf and floor
Rework access	Generally easier	Often restricted
Packaging potential	Moderate	Higher I/O integration

The multi-tier approach is justified when additional packaging density offsets the greater machining and assembly complexity.

High-Speed and HDI Integration

A high speed PCB with a recessed die may reduce interconnection length, but cavity geometry introduces discontinuities that require simulation.

For example, a 100 Ω differential interface routed near a cavity edge needs continuous reference-plane support.

Removing copper beneath a trace changes its electromagnetic environment and may alter impedance.

An HDI PCB can use laser microvias to connect bonding shelves to internal routing layers.

Representative dimensions include:

Laser microvia diameter: 100 μm.
Microvia dielectric depth: 60 μm.
Fine-line routing: 50/50 μm.
Mechanical finished hole: 0.20 mm.
Differential impedance target: 100 Ω ±10%.

Microvias should not be placed where subsequent cavity milling could expose or weaken their barrels.

Representative Factory Case

Eight-Layer Multi-Tier Module

The following is a representative engineering case using industry-plausible parameters. It is not an authenticated production order or measured factory yield report.

An eight-layer module requires a recessed semiconductor die and two surrounding bonding elevations.

Parameter	Initial design
Copper layers	18
Finished board thickness	2.40 mm
Cavity levels	3
Shelf 1 depth	0.50 mm
Shelf 2 depth	1.00 mm
Die floor depth	1.45 mm
Minimum line/space	75/75 μm
Finished mechanical hole	0.20 mm
Impedance requirement	50 Ω ±10%
Initial floor tolerance	±0.10 mm

Manufacturing Review

Three potential failures are identified:

Separate Z-datums create ambiguity in shelf elevations.
Copper features are positioned 0.10 mm from a routed wall, leaving insufficient machining allowance.
The specified floor tolerance may be too large for the proposed die-attach and bonding process.

Revised Construction

The engineering revision establishes:

One finished-top-surface datum for all depths.
A 0.35 mm nominal copper-to-wall clearance.
A cavity-floor depth tolerance target of ±0.05 mm.
Local surface mapping before precision milling.
Separate inspection of each shelf and die floor.

Reducing the specified depth tolerance from ±0.10 to ±0.05 mm cuts the allowed total depth variation from 0.20 to 0.10 mm, a 50% reduction.

Increasing copper-to-wall clearance from 0.10 to 0.35 mm adds 0.25 mm of nominal separation.

These are quantifiable design changes, not verified production improvements. Actual machining capability, bond yield, and cavity flatness must be demonstrated with trial panels.

Manufacturing and Assembly Flow

A controlled multi-step cavity process can follow this sequence:

Review the stackup, cavity drawing, and assembly model.
Fabricate and inspect inner copper layers.
Laminate the multilayer construction.
Drill and plate required interconnections.
Complete circuitry and selected surface finishes.
Fixture the panel and measure its topography.
Mill each cavity level using the approved Z-datum.
Inspect pocket geometry, remaining web, and floor condition.
Clean the cavity and verify bonding-pad surfaces.
Attach semiconductor dies and cure adhesive.
Perform wire bonding and bond-strength testing.
Apply encapsulation or lid sealing where specified.
Complete electrical testing and dimensional inspection.

The actual order of cavity formation and metallization depends on whether the construction uses exposed internal copper, plated shelves, or preformed laminated openings.

Process Control and Testing

Quality control should separate bare-board measurements from semiconductor assembly verification.

Bare-board inspection

Depth measurements at defined X/Y locations.
Optical or coordinate measurement of pocket dimensions.
Internal corner-radius inspection.
Local floor flatness verification.
Microsection analysis of critical residual webs.
Copper continuity and isolation testing.
Bow and twist measurement.

Assembly inspection

Die placement and adhesive coverage.
Bond-pad cleanliness and finish verification.
Wire-loop height measurement.
Bond pull or shear testing using qualified criteria.
Optical inspection of adjacent wires.
Encapsulation height and void inspection.
Functional electrical testing.

For critical RF assemblies, S-parameter measurements may also be required.

Common Design Errors

Multiple Z-Datums

Independent depth references create tolerance conflicts. Use one controlling datum and clearly identify the finished surface condition.

Missing Corner Radii

A square internal pocket cannot be produced with a round milling cutter without corner relief or another machining process.

Insufficient Residual Web

A thin dielectric floor can crack during routing, die attachment, or handling. Confirm the remaining structure against the actual cavity span.

Incorrect Bond Pad Finish

A solderable finish is not necessarily wire-bondable. Specify and qualify the pad metallurgy before fabrication.

Ignoring Wire-Loop Clearance

Bond wires may collide with cavity walls, neighboring loops, encapsulation features, or the package lid.

Unbalanced Copper Removal

Large asymmetric pockets can increase panel distortion. Evaluate copper distribution, fixture support, and the manufacturing sequence.

Missing Inspection Requirements

A cavity drawing without defined depth measurement points, floor flatness, or surface conditions leaves acceptance criteria ambiguous.

Frequently Asked Questions

Q1. What is a multi-step cavity PCB?

A multi-step cavity PCB is a multilayer circuit board with two or more recessed platforms at controlled depths. It supports embedded components, semiconductor dies, and multi-tier wire bonding. Each elevation requires defined dimensions, material clearances, and inspection criteria.

Q2. What depth tolerance is achievable?

Representative controlled-depth milling targets range from ±0.10 mm to ±0.05 mm, depending on the board construction, fixture, tool, and measurement method. Tighter tolerances require process qualification and may not be available across large cavities or uneven panels.

Q3. Can wire bonding pads be placed inside cavities?

Yes. Bonding pads can be located on cavity floors or intermediate shelves when their surface finish, pad geometry, cleanliness, and bonding access are qualified. Gold-wire bonding typically requires a specifically approved metallization rather than an unspecified solder finish.

Q4. Can multi-step cavities support HDI and high-speed circuits?

Yes. HDI microvias and fine-line routing can connect cavity shelves to internal layers. High-speed designs must also control reference-plane continuity, via transitions, and impedance near removed dielectric regions. Electrical simulation and representative testing are required for critical interfaces.

Conclusion

A multi-step cavity PCB integrates mechanical packaging and electrical interconnection through multiple precisely controlled recesses.

Its success depends on a common Z-datum, qualified milling tolerances, balanced laminate construction, adequate residual thickness, appropriate bonding metallurgy, and a complete inspection plan.

For wire-bonded HDI and high-speed applications, cavity geometry, electrical routing, and assembly requirements must be designed together rather than treated as separate manufacturing operations.